1. Field of the Invention
The present invention relates to methods of forming semiconductor devices, and, more particularly, to methods of forming a multi-bridge-channel metal oxide semiconductor field effect transistor (MBCFET).
2. Description of the Related Art
As the integration density of semiconductor memory devices has increased, the area of an active region where elements are disposed has gradually been scaled down. The downscaling of the active region may preclude obtaining a sufficient effective channel length or effective channel width of a transistor.
A reduction in the channel length of a transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), may make a short channel effect predominant, thus adversely affecting the characteristics of the transistor. Also, as the channel width of a transistor decreases, a narrow width effect, which results in an increase of threshold voltage, may become more prominent and have a bad influence on the transistor. To overcome these drawbacks, many attempts for increasing the effective channel length (or width) of a transistor within a restricted active region have been made.
For example, a multi-bridge-channel FET (MBCFET) was presented. The MBCFET includes a plurality of rectangular thin channels and a gate surrounding the top, bottom, and side surfaces of the channels, and the channels are vertically stacked. The gate disposed on the channels includes branch layers that extend between the channels. The branch layers of the gate are connected to each other on two opposite lateral portions of the channels.
A typical MBCFET has the above-described structure, but a process of manufacturing the MBCFET may include some problems. For example, to operate an MBCFET, source and drain regions are connected to channels. However, when a stacked structure including the channels and a gate and/or branch layers is formed, a top of the source and drain regions is disposed in an even lower position than a top layer of the gate, thus leaving a step difference therebetween.
FIG. 1 is a cross-sectional view of a conventional MBCFET structure. Referring to FIG. 1, the conventional MBCFET includes a plurality of rectangular thin channels 11 disposed on a substrate 10, a gate 30 surrounding the top and bottom surfaces and/or the front and rear surfaces of the channels 11, and branch layers 31 of the gate 30. Gate dielectric layers 20 are disposed between the gate 30 (and/or the branch layers 31) and the channels 11.
The channels 11 are electrically connected to source and drain regions 15. When the channels 11 and the gate 30 (and/or the branch layers 31) are stacked,the source and drain regions 15 are disposed in a much lower position than a top layer of the gate 30. To overcome this step difference and electrically connect the source and drain regions 15 and the channels 11, a connection layer 13 is formed in the form of spacers on the sidewalls of the stacked structure including the channels 11 and the branch layers 31.
Thus, charges are transported between a contact position 17 on the source and drain regions 15 and the top layer of the gate 30 through the connection layer 13 that electrically connects the source and drain regions 15 and the channels 11. In this case, a charge transfer distance is greatly extended so that resistances to the source and drain regions 15 are undesirably increased.
Also, if the substrate 10 is a silicon on insulator (SOI) substrate, to realize a thin body of the SOI substrate, a silicon layer may be formed to a thickness of about 30 nm or less on a buried oxide layer or a bottom oxide layer (BOX). In this case, the buried oxide layer or the BOX may be exposed because an over etch margin is insufficient in an etch process for forming a path required for forming the branch layers 31. The exposure of the buried oxide layer or the BOX may preclude performing selective epitaxial growth (SEG). Accordingly, it may become difficult to form the source and drain regions 15.
Moreover, owing to the step difference between the source and drain regions 15 and the top layer of the gate 30, it may be difficult to perform a subsequent metallization, which is required to selectively form a metal electrode layer at the contact position 17 on the source and drain regions 15. This is because the step difference impedes forming insulating spacers, which are used in forming a metal layer or/a metal silicide layer selectively on the connection layer 13.
To solve these problems, a process of forming a polysilicon plug for the source and drain regions 15 on the connection layer 13 can be considered. FIG. 2 is a cross-sectional view of a conventional MOSFET including polysilicon-plug type source and drain regions 55. Referring to FIG. 2, the polysilicon-plug type source and drain regions 55 are formed on a stacked structure, which is formed on a substrate 50 and includes a plurality of rectangular thin channels 51, a gate 70, and branch layers 71 of the gate 70. The channels 51, between which the branch layers 71 and gate dielectric layers 60 are interposed, are connected to the source and drain regions 55 by a connection layer 53. In this case, the source and drain regions 55 are formed using polysilicon plugs 57 so as to reduce a step difference between the source and drain regions 55 and the gate 70.
However, the foregoing structure assists in reducing the step difference, but makes a manufacturing process complicated because the manufacturing process involves depositing and etching back a polysilicon layer. Also, corners of the channel 51 disposed under the gate 70 may be etched in the etchback process of the polysilicon layer so that upper shoulder corners 59 of the connection layer 53 have steep etched surfaces. Due to the steep etched surfaces of the connection layer 53, lightly doped drain (LDD)-type source and drain regions 55 formed in the connection layer 53 also have steep profiles. In this case, resistances of the source and drain regions 55 are undesirably increased. Further, by etching the corners of the channel 51, an etchback margin may be insufficient.
As described above, the step difference between the source and drain regions and the top layer of the gate may lead to an increase in resistance. Thus, there remains room for improvement in the art.